00:00.0 Class 0600: 1166:0005 (rev 03)
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR-
	Latency: 64, cache line size 08

00:06.0 Class 0300: 1013:00a0 (rev 22)
	Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Interrupt: pin A routed to IRQ 0
	Region 0: Memory at ae000000 (32-bit, prefetchable) [size=16M]
	Expansion ROM at <unassigned> [disabled] [size=16M]

00:08.0 Class 0100: 1000:000f (rev 04)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 255 (4250ns min, 16000ns max), cache line size 08
	Interrupt: pin A routed to IRQ 9
	Region 0: I/O ports at 6000 [size=256]
	Region 1: Memory at afffdf00 (32-bit, non-prefetchable) [size=256]
	Region 2: Memory at affff000 (32-bit, non-prefetchable) [size=4K]

00:0b.0 Class 0200: 10b8:0005 (rev 08)
	Subsystem: 10b8:a011
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 64 (2000ns min, 7000ns max)
	Interrupt: pin A routed to IRQ 5
	Region 0: I/O ports at 6400 [size=256]
	Region 1: Memory at afffe000 (32-bit, non-prefetchable) [size=4K]
	Expansion ROM at <unassigned> [disabled] [size=64K]
	Capabilities: [dc] Power Management version 1
		Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0-,D1+,D2+,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:0f.0 Class 0602: 0e11:0001 (rev 07)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0

00:11.0 Class 0600: 1166:0005 (rev 03)
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR-
	Latency: 64, cache line size 08

01:07.0 Class 0280: 0e11:ae43 (rev 10)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 64, cache line size 08
	Interrupt: pin A routed to IRQ 10
	Region 0: I/O ports at 7400 [size=16]
	Region 1: Memory at c6dfeef0 (32-bit, non-prefetchable) [size=16]
	Expansion ROM at <unassigned> [disabled] [size=64K]

01:09.0 Class 0100: 1000:000f (rev 04)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 255 (4250ns min, 16000ns max), cache line size 08
	Interrupt: pin A routed to IRQ 11
	Region 0: I/O ports at 7000 [size=256]
	Region 1: Memory at c6dfef00 (32-bit, non-prefetchable) [size=256]
	Region 2: Memory at c6dff000 (32-bit, non-prefetchable) [size=4K]

01:0a.0 Class 0604: 1014:0022 (rev 07)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 128, cache line size 08
	Bus: primary=01, secondary=02, subordinate=02, sec-latency=248
	I/O behind bridge: 00008000-00008fff
	Memory behind bridge: c6e00000-c6efffff
	Prefetchable memory behind bridge: b0000000-b7ffffff
	BridgeCtl: Parity+ SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B-

01:0d.0 Class 0604: 1014:0022 (rev 07)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 128, cache line size 08
	Bus: primary=01, secondary=03, subordinate=03, sec-latency=248
	I/O behind bridge: 00009000-00009fff
	Memory behind bridge: c6f00000-c6ffffff
	Prefetchable memory behind bridge: b8000000-bfffffff
	BridgeCtl: Parity+ SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B-

02:00.0 Class 0180: 0e11:ae10 (rev 03)
	Subsystem: 0e11:4034
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0, cache line size 08
	Interrupt: pin A routed to IRQ 15
	Region 0: I/O ports at 8000 [size=256]
	Region 1: Memory at c6efff00 (32-bit, non-prefetchable) [size=256]
	Region 2: Memory at b0000000 (32-bit, prefetchable) [size=128M]
	Expansion ROM at <unassigned> [disabled] [size=16K]

03:00.0 Class 0180: 0e11:ae10 (rev 03)
	Subsystem: 0e11:4030
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0, cache line size 08
	Interrupt: pin A routed to IRQ 15
	Region 0: I/O ports at 9000 [size=256]
	Region 1: Memory at c6ffff00 (32-bit, non-prefetchable) [size=256]
	Region 2: Memory at b8000000 (32-bit, prefetchable) [size=128M]
	Expansion ROM at <unassigned> [disabled] [size=16K]